The present invention relates generally to synthesis of integrated circuits and more particularly to synthesis of datapaths in integrated circuits.
The development of the integrated circuit (IC) chip has been integral to the improvement and advancement of many industries. As the complexity and functionality of these ICs has increased, their incorporation into a variety of products has likewise increased. While in some situations, a designer is able to use standard ICs for a desired application, in other situations standard chips are unable to meet the precise needs of a designer. In such situations, designers often turn to an application specific integrated circuit (ASIC).
ASICs allow a designer to design a circuit with specifications and functionality closely tailored to their desired product application, without having to conform their product to the feature and performance limits of a standard chip. Typically, ASIC production begins with a set of circuit specifications. This design is then written in a hardware description language (HDL), such as VHDL.RTM., the IEEE standard. The description is then "synthesized", i.e., a computer program uses the set of circuit specifications encoded in an HDL to design the circuitry of the IC. Next, the behavior of the circuit is verified and, ultimately, a circuit layout is created. From the layout, a mask is formed and used for the IC chip (ASIC) production.
In copending U.S. patent Ser. No. 07/877,951, referenced above, a datapath synthesizer converts an HDL circuit specification into a datapath netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic and random ("control") logic. The random logic is implemented using gates from a gate library (for example a standard cell or gate array library) using a logic synthesizer. The datapath logic is optimally synthesized using a datapath synthesizer having a library of datapath components ("cells").
The problem encountered is how to optimally synthesize an IC HDL specification. Previously, datapath synthesis tools were able to map HDL specification only to combinational datapath components and memory elements (such as flip-flops and latches) in the datapath Library. Previous datapath synthesis tools could not map HDL specifications implying sequential logic to sequential components in the library. Instead, combinational components and memory elements such as such as (such as flip-flops and latches) were used.
For example, if a counter (which is sequential logic) was implied by the HDL specification, and a counter component (which is a sequential component) existed in the library, previous tools were unable to map the counter component. Instead, a counter was built using an adder or incrementor and a flip-flop register, which tended to be, a non-optimal solution.